library verilog;
use verilog.vl_types.all;
entity zl_2346_5 is
    port(
        en              : in     vl_logic;
        RA              : in     vl_logic_vector(1 downto 0);
        Wr              : in     vl_logic;
        Rd              : in     vl_logic;
        M               : in     vl_logic_vector(1 downto 0);
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        datain          : in     vl_logic_vector(3 downto 0);
        sel             : out    vl_logic_vector(2 downto 0);
        seg             : out    vl_logic_vector(7 downto 0)
    );
end zl_2346_5;
